UPD78F9500MA-CAC-A Datasheet, PDF (156/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
Figure 8-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by
Software” Is Selected by Option Byte
Reset
WDTE = “ACH”
Clear WDT counter.
WDT clock: fRL
Overflow time: 546.13 ms (MAX.)
WDT clock = fX
Select overflow time
(settable only once).
WDTE = “ACH”
Clear WDT counter.
WDT clock = fRL
Select overflow time
(settable only once).
WDCS4 = 1
WDT operation stops.
WDTE = “ACH”
Clear WDT counter.
WDT clock: fX
Overflow time: 2¹³/fX to 2²⁰/fX
WDT count continues.
HALT
instruction
STOP
instruction
Interrupt
Interrupt
HALT
WDT count stops.
STOP
WDT count stops.
WDT clock: fRL
LSRSTOP = 1
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
LSRSTOP = 0
HALT instruction
WDT clock: fRL
WDT count stops.
HALT
instruction
Interrupt
STOP
instruction
Interrupt
STOP
instruction
Interrupt
Interrupt
HALT
WDT count stops.
STOP
WDT count stops.
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User’s Manual U18172EJ3V0UD