UPD78F9500MA-CAC-A Datasheet, PDF (329/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(6/15)
Page
16-bit
Timer start
timer/
errors
event
counters _{One-shot pulse}
00
output
(μPD78F9
20x only)
Capture
operation
Changing
compare
register during
timer operation
External event
counter
External clock
limitation
8-bit timer CMP01: 8-bit
H1
timer H
compare
register 01
CMP11: 8-bit
timer H
compare
register 11
TMHMD1: 8-bit
timer H mode
register 1
PWM output
An error of up to one clock may occur in the time required for a match signal to be p. 124
generated after timer start. This is because 16-bit timer counter 00 (TM00) is
started asynchronously to the count clock.
One-shot pulse output normally operates only in the free-running mode or in the
clear & start mode at the valid edge of the TI000 pin. Because an overflow does
not occur in the clear & start mode on a match between TM00 and CR000, one-
shot pulse output is not possible.
p. 125
When the CRC001 bit value is 1, capture is not performed in the CR000 register if p. 127
both the rising and falling edges have been selected as the valid edges of the
TI000 pin.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input from
the TI010 pin can be used as an external interrupt source because INTTM000 is
generated at that timing.
p. 127
With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare p. 128
register, when changing CR0n0 around the timing of a match between 16-bit timer
counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during
timer counting, the change timing may conflict with the timing of the match, so the
operation is not guaranteed in such cases. To change CR0n0 during timer
counting, INTTM000 interrupt servicing performs the following operation.
If CR010 is changed during timer counting without performing processing <1>
above, the value in CR010 may be rewritten twice or more, causing an inversion
of the output level of the TO00 pin at each rewrite.
p. 128
The timing of the count start is after two valid edge detections.
p. 129
When using an input pulse of the TI000 pin as a count clock (external trigger), be
sure to input the pulse width which satisfies the AC characteristics. For the AC
characteristics, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS.
p. 130
When an external waveform is input to 16-bit timer/event counter 00, it is sampled p. 130
by the noise limiter circuit and thus an error occurs on the timing to become valid
inside the device.
CMP01 cannot be rewritten during timer count operation.
p. 133
In the PWM output mode, be sure to set CMP11 when starting the timer count
operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0)
(be sure to set again even if setting the same value to CMP11).
p. 133
When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. p. 135
In the PWM output mode, be sure to set 8-bit timer H compare register 11
p. 135
(CMP11) when starting the timer count operation (TMHE1 = 1) after the timer
count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the
same value to the CMP11 register).
In PWM output mode, the setting value for the CMP11 register can be changed
during timer count operation. However, three operation clocks (signal selected
using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to
transfer the register value after rewriting the CMP11 register value.
p. 141
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure
to set again even if setting the same value to the CMP11 register).
p. 141
User’s Manual U18172EJ3V0UD
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