UPD78F9500MA-CAC-A Datasheet, PDF (306/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 19 ELECTRICAL SPECIFICATIONS
<R> A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V^{Note 1}, VSS = 0 V^{Note 2}) (μPD78F920x only)
(1) A/D converter basic characteristics
Parameter
Symbol
Conditions
Resolution
Conversion time
Analog input voltage
tCONV
VAIN
4.5 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD < 4.5 V
2.85 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 2.85 V
MIN.
10
3.0
4.8
6.0
14.0
V Note 2
SS
TYP.
10
MAX.
Unit
10
bit
100
μs
100
μs
100
μs
100
μs
VDD
V
(2) A/D Converter Characteristics (high-speed internal oscillation clock)
Parameter
Overall error^{Notes 3, 4}
Zero-scale error^{Notes 3, 4}
Full-scale error^{Notes 3, 4}
Integral non-linearity error^{Note 3}
Differential non-linearity error^{Note 3}
Symbol
AINL
Ezs
Efs
ILE
DLE
Conditions
MIN.
TYP.
MAX.
−0.1 to +0.2^{Note 5} −0.35 to +0.45
−0.1 to +0.2^{Note 5} −0.35 to +0.45
−0.1 to +0.2^{Note 5} −0.35 to +0.40
±1^{Note 5}
±3
±1^{Note 5}
±1.5
Unit
%FSR
%FSR
%FSR
LSB
LSB
(3) A/D Converter Characteristics (Crystal/Ceramic Oscillation Clock, External Clock)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Overall error^{Notes 3, 4}
Zero-scale error^{Notes 3, 4}
Full-scale error^{Notes 3, 4}
AINL
Ezs
Efs
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
−0.20 to +0.35^{Note 5} −0.35 to +0.65
±0.25^{Note 5}
−0.35 to +0.55
−0.20 to +0.35^{Note 5} −0.35 to +0.65
±0.25^{Note 5}
−0.35 to +0.55
−0.20 to +0.35^{Note 5} −0.35 to +0.55
%FSR
%FSR
%FSR
%FSR
%FSR
Integral non-linearity error^{Note 3}
ILE
Differential non-linearity error^{Note 3} DLE
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
±0.25^{Note 5}
±1.5^{Note 5}
±1.5^{Note 5}
±1.0^{Note 5}
±1.0^{Note 5}
−0.35 to +0.50
±3.0
±4.0
±2.5
±2.5
%FSR
LSB
LSB
LSB
LSB
Notes 1.
2.
3.
4.
5.
In μPD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the
A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
In μPD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (%FSR) to the full-scale value.
A value when HALT mode is set by an instruction immediately after A/D conversion starts.
Caution The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port
or if the level of a port that is not used for A/D conversion is changed during A/D conversion.
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User’s Manual U18172EJ3V0UD