UPD78F9500MA-CAC-A Datasheet, PDF (150/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
8.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Item
Control registers
Table 8-3. Configuration of Watchdog Timer
Configuration
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 8-1. Block Diagram of Watchdog Timer
fRL/2²
fX/2⁴
Clock
input
controller
2
16-bit
counter
2¹¹/fRL to
2¹⁸/fRL
or
2¹³/fX to
2²⁰/fX
Clear
Selector
3
Output
controller
Internal reset signal
Watchdog timer enable
register (WDTE)
0
1
1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0
Watchdog timer mode
register (WDTM)
Internal bus
Option byte
(to set “low-speed
internal oscillator cannot be
stopped” or “low-speed
internal oscillator can be
stopped by software”)
Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency
2. fX: System clock oscillation frequency
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User’s Manual U18172EJ3V0UD