UPD78F9500MA-CAC-A Datasheet, PDF (277/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 16 FLASH MEMORY
Figure 16-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized
(from Write to Internal Verify)
Write to internal verify
<1> Set source data for write
Figure 16-22
<1> to <4>
Figure 16-18
<1> to <7>
<2> Specify byte write command
<3> Shift to self programming
mode
Figure 16-22
<5> to <10>
Figure 16-19
<1> to <6>
<4> Execute byte write command
<4> Check execution result ^Abnormal
(VCERR and WEPRERR flags)
Normal
<5> Shift to normal mode
Yes
<6> All data written?
No
Figure 16-23
<1> to <5>
Figure 16-18
<1> to <7>
<7> Specify internal verify command
<8> Shift to self programming
mode
Figure 16-23
<6> to <11>
Figure 16-19
<1> to <6>
<9> Execute internal verify command
<9> Check execution result Abnormal
(VCERR and WEPRERR flags)
Normal
<10> Shift to normal mode
Normal termination
Abnormal termination^Note
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <10> in Figure 16-28 correspond to <1> to <10> in 16.8.11 (2) (previous page).
User’s Manual U18172EJ3V0UD
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