UPD78F9500MA-CAC-A Datasheet, PDF (207/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 13 POWER-ON-CLEAR CIRCUIT
13.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 13-1.
Figure 13-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
13.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.1 V) are compared,
and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD ≥ VPOC.
Figure 13-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (VDD)
POC detection voltage
(VPOC = 2.1 V ±0.1 V)
Internal reset signal
Time
User’s Manual U18172EJ3V0UD
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