UPD78F9500MA-CAC-A Datasheet, PDF (88/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 5 CLOCK GENERATORS
(3) External clock input circuit
If external clock input is selected by the option byte, the following is possible.
• High-speed operation
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
• Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin.^Note For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Note μPD78F920x only
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
Figure 5-12. Timing of Default Start by External Clock Input
(a)
VDD
RESET _H
Internal reset
(b)
System clock
CPU clock
External clock input
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stops^Note)
Note Operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
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User’s Manual U18172EJ3V0UD