UPD78F9500MA-CAC-A Datasheet, PDF (211/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 14 LOW-VOLTAGE DETECTOR
14.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detect register (LVIM)
• Low-voltage detection level select register (LVIS)
(1) Low-voltage detect register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H^{Note 1}.
Figure 14-2. Format of Low-Voltage Detect Register (LVIM)
Address: FF50H After reset: 00H^{Note 1} R/W^{Note 2}
Symbol
<7>
6
5
4
3
2
<1>
<0>
LVIM
LVION
0
0
0
0
0
LVIMD
LVIF
LVION^{Note 3}
0
Disable operation
1
Enable operation
Enabling low-voltage detection operation
LVIMD
0
1
Low-voltage detection operation mode selection
Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI)
Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIF^{Note 4}
Low-voltage detection flag
0
Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is disabled
1
Supply voltage (VDD) < detection voltage (VLVI)
Notes 1.
2.
3.
4.
For a reset by LVI, the value of LVIM is not initialized.
Bit 0 is a read-only bit.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Be sure to set bits 2 to 6 to 0.
User’s Manual U18172EJ3V0UD
209