UPD78F9500MA-CAC-A Datasheet, PDF (326/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(3/15)
Page
16-bit
timer/
event
counters
00
CR000: 16-bit
timer capture/
compare
register 000
(μPD78F9
20x only)
The value of CR000 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR000 set in compare mode
even if a capture trigger is input.
When P21 is used as the input pin for the valid edge of TI010, it cannot be used
as a timer output (TO00). Moreover, when P21 is used as TO00, it cannot be
used as the input pin for the valid edge of TI010.
pp. 93,
125
pp. 93,
127
pp. 93,
129
If the register read period and the input of the capture trigger conflict when CR000 pp. 93,
is used as a capture register, the capture trigger input takes precedence and the 126
read data is undefined. Also, if the count stop of the timer and the input of the
capture trigger conflict, the capture trigger is undefined.
Changing the CR000 setting may cause a malfunction. To change the setting,
refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
p. 93
CR010: 16-bit
capture/
compare
register 010
In the free-running mode and in the clear & start mode using the valid edge of the pp. 94,
TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated 124
when CR010 changes from 0000H to 0001H following overflow (FFFFH).
If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00),
TM00 continues counting, overflows, and then starts counting from 0 again. If the
new value of CR010 is less than the old value, therefore, the timer must be reset
to be restarted after the value of CR010 is changed.
pp. 94,
124
The value of CR010 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
pp. 94,
125
The capture operation may not be performed for CR010 set in compare mode
even if a capture trigger is input.
pp. 94,
127
If the register read period and the input of the capture trigger conflict when CR010 pp. 94,
is used as a capture register, the capture trigger input takes precedence and the 126
read data is undefined. Also, if the timer count stop and the input of the capture
trigger conflict, the capture data is undefined.
Changing the CR010 setting during TM00 operation may cause a malfunction. To p. 95
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
TMC00: 16-bit
timer mode
control register
00
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and
TMC003 (operation stop mode) are set to a value other than 0, 0, respectively.
Set TMC002 and TMC003 to 0, 0 to stop the operation.
The timer operation must be stopped before writing to bits other than the OVF00
flag.
pp. 95,
124
pp. 96,
125
If the timer is stopped, timer counts and timer interrupts do not occur, even if a
signal is input to the TI000/TI010 pins.
pp. 96,
124
Except when TI000 pin valid edge is selected as the count clock, stop the timer
operation before setting STOP mode or system clock stop mode; otherwise the
timer may malfunction when the system clock starts.
pp. 96,
129
Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 pp. 96,
(PRM00) after stopping the timer operation.
125
If the clear & start mode entered on a match between TM00 and CR000, clear & pp. 96,
start mode at the valid edge of the TI000 pin, or free-running mode is selected, 126
when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH
to 0000H, the OVF00 flag is set to 1.
324
User’s Manual U18172EJ3V0UD