UPD78F9500MA-CAC-A Datasheet, PDF (263/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 16 FLASH MEMORY
Figure 16-24. Example of Internal Verify 2 Operation in Self Programming Mode
Internal verify 2
<1> Set internal verify 2
command (FLCMD = 02H)
<2> Set No. of block for
internal verify, to FLAPH
<3> Sets FLAPL to the start address
<4> Set the same value as
that of FLAPH to FLAPHC
<5> Sets FLAPLC to the end address
<6> Clear PFS
<7> Clear & restart WDT counter
(WDTE = ACH)^Note
<8> Execute HALT instruction
<9> Check execution result
(VCERR and WEPRERR flags)
Normal
<11> Normal termination
Abnormal
<10> Abnormal termination
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11> in Figure 16-24 correspond to Internal verify 2 <1> to <11> in 16.8.9 (the page before last).
User’s Manual U18172EJ3V0UD
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