UPD78F9500MA-CAC-A Datasheet, PDF (201/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 12 RESET FUNCTION
Figure 12-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed internal oscillation clock or external clock input
High-speed internal oscillation clock or
external clock input
CPU clock
Watchdog overflow
Normal operation
in progress
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Internal reset signal
<R>
Port pin
Hi-Z
Note The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
<2> With crystal/ceramic oscillation clock (μPD78F920x only)
Crystal/ceramic
oscillation clock
CPU clock
Watchdog overflow
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (2¹⁰/fX to 2¹⁷/fX)
Normal operation
(reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Internal reset signal
Port pin
Hi-Z
Note The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark fX: System clock oscillation frequency
User’s Manual U18172EJ3V0UD
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