UPD78F9500MA-CAC-A Datasheet, PDF (241/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 16 FLASH MEMORY
(2) Flash protect command register (PFCMD)
If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an
operation to write the flash programming mode control register (FLPMC) may have a serious effect on the
system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop
inadvertently.
Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.
<1> Write a specific value to PFCMD (A5H)
<2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid)
<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is
invalid)
<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)
Caution
Interrupt servicing cannot be executed in self-programming mode. Disable interrupt
servicing (by executing the DI instruction while MK0 = FFH) before executing the specific
sequence that sets self-programming mode and after executing the specific sequence that
changes the mode to the normal mode.
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
Check FPRERR using a 1-bit memory manipulation instruction.
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set by an 8-bit memory manipulation instruction.
Reset signal generation makes PFCMD undefined.
Figure 16-11. Format of Flash Protect Command Register (PFCMD)
Address: FFA0H After reset: Undefined
Symbol
7
6
5
PFCMD REG7
REG6
REG5
W
4
REG4
3
REG3
2
REG2
1
REG1
0
REG0
(3) Flash status register (PFS)
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self-programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
Caution Check FPRERR using a 1-bit memory manipulation instruction.
User’s Manual U18172EJ3V0UD
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