UPD78F9500MA-CAC-A Datasheet, PDF (187/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 10 INTERRUPT FUNCTIONS
Figure 10-9. Example of Multiple Interrupts (2/2)
Example 3. A priority is controlled by the Multiple interrupts
The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1.
(Interruption priority INTP0 > INTP1 > INTTMH1 (refer to Table10-1))
Main processing
INTTNH1 servicing
EI
IE = 0
INTTMH1
PMK0 = 1
EI
IE = 0
INTP1 servicing
INTP0
INTP1
RETI
PMK0 = 0
IE = 0
INTP0 servicing
RETI
RETI
In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the
INTP0 interrupt was first masked.
Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is
performed.
IE = 0: Interrupt request acknowledgment disabled
10.4.3 Interrupt request pending
Some instructions may keep pending the acknowledgment of an instruction request until the completion of the
execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated
during the execution. The following shows such instructions (interrupt request pending instruction).
• Manipulation instruction for interrupt request flag register 0 (IF0)
• Manipulation instruction for interrupt mask flag register 0 (MK0)
User’s Manual U18172EJ3V0UD
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