UPD78F9500MA-CAC-A Datasheet, PDF (96/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY)
(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control
register 00 (CRC00).
CR010 is set by 16-bit memory manipulation instruction.
Reset signal generation clears CR010 to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
Address: FF16H, FF17H After reset: 0000H R/W
Symbol
CR010
FF17H
76543210
FF16H
76543210
• When CR010 is used as a compare register
The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match.
• When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
means of prescaler mode register 00 (PRM00) (refer to Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 Capture Trigger
TI000 Pin Valid Edge
ES010
Falling edge
Falling edge
0
Rising edge
Rising edge
0
Both rising and falling edges
Both rising and falling edges
1
Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002:
Bit 2 of capture/compare control register 00 (CRC00)
ES000
0
1
1
Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000
pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010
changes from 0000H to 0001H following overflow (FFFFH).
2. If the new value of CR010 is less than the value of 16-bit timer counter 00 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR010 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR010 is changed.
3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR010 set in compare mode even if a
capture trigger is input.
5. If the register read period and the input of the capture trigger conflict when CR010 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the timer count stop and the input of the capture trigger conflict,
the capture data is undefined.
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User’s Manual U18172EJ3V0UD