UPD78F9500MA-CAC-A Datasheet, PDF (223/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 15 OPTION BYTE
Figure 15-3. Format of Option Byte (μPD78F920x) (2/2)
LIOCP
Low-speed internal oscillates
1
Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit)
0
Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit)
Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to
the watchdog timer (WDT) is fixed to low-speed internal oscillation clock.
2. If it is selected that low-speed internal oscillator can be stopped by software, supply of
the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of
bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly,
clock supply is also stopped when a clock other than the low-speed internal oscillation
clock is selected as a count clock to WDT.
While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be
supplied to the 8-bit timer H1 even in the STOP mode.
Remarks 1. ( ): fX = 10 MHz
2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator
to be used.
3. An example of software coding for setting the option bytes is shown below.
OPB CSEG AT 0080H
DB 10010001B
; Set to option byte
; Low-speed internal oscillator cannot be stopped
; The system clock is a crystal or ceramic resonator.
; The RESET pin is used as an input-only port pin (P34).
; Minimum oscillation stabilization time (2¹⁰/fX)
4. For details on the timing at which the option byte is referenced, see CHAPTER 12 RESET
FUNCTION.
User’s Manual U18172EJ3V0UD
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