UPD78F9500MA-CAC-A Datasheet, PDF (184/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 10 INTERRUPT FUNCTIONS
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
Figure 10-6 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
Figure 10-6. Interrupt Request Acknowledgment Processing Algorithm
Start
No
××IF = 1?
Yes (Interrupt request generated)
No
××MK = 0?
Yes
IE = 1?
Interrupt request pending
No
Yes
Vectored interrupt
servicing
Interrupt request pending
××IF:
××MK:
IE:
Interrupt request flag
Interrupt mask flag
Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
Figure 10-7. Interrupt Request Acknowledgment Timing (Example of MOV A, r)
Clock
8 clocks
CPU
MOV A, r
Saving PSW and PC, jump
to interrupt servicing
Interrupt servicing program
Interrupt
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
the interrupt is acknowledged after the instruction under execution is complete. Figure 10-7 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the instruction fetch starts, the interrupt acknowledgment
processing is performed after the MOV A, r instruction is executed.
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User’s Manual U18172EJ3V0UD