UPD78F9500MA-CAC-A Datasheet, PDF (149/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode
Option Byte Setting
Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software
Watchdog timer clock
source
Operation after reset
Fixed
to
f ^Note
RL
1_.
• Selectable by software (fX, fRL or stopped)
• When reset is released: fRL
Operation starts with the maximum interval (2¹⁸/fRL). Operation starts with the maximum interval
(2¹⁸/fRL).
Operation mode
selection
Features
The interval can be changed only once.
The watchdog timer cannot be stopped.
The clock selection/interval can be changed only
once.
The watchdog timer can be stopped^{Note 2}.
Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset
period).
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock
source of the watchdog timer.
<1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following conditions.
• When fX is stopped
• In HALT/STOP mode
• During oscillation stabilization time
<2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions.
• If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction
• In HALT/STOP mode
Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency
2. fX: System clock oscillation frequency
User’s Manual U18172EJ3V0UD
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