UPD78F9500MA-CAC-A Datasheet, PDF (186/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 10 INTERRUPT FUNCTIONS
Figure 10-9. Example of Multiple Interrupts (1/2)
Example 1. Multiple interrupts are acknowledged
Main processing
INTxx servicing
INTyy servicing
IE = 0
EI
IE = 0
EI
INTxx
INTyy
RETI
RETI
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
Before each interrupt request acknowledgement, the EI instruction is issued, the interrupt mask is released, and the
interrupt request acknowledgement enable state is set.
Caution Multiple interrupts can be acknowledged even for low-priority interrupts.
Example 2. Multiple interrupts are not generated because interrupts are not enabled
Main processing
INTxx servicing
INTyy servicing
EI
INTxx
IE = 0
INTyy
RETI
INTyy is held pending
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgment disabled
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User’s Manual U18172EJ3V0UD