UPD78F9500MA-CAC-A Datasheet, PDF (261/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 16 FLASH MEMORY
16.8.9 Example of internal verify operation in self programming mode
An example of the internal verify operation in self programming mode is explained below.
• Internal verify 1
<1> Set 01H (internal verify 1) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the flash address pointer L (FLAPL) to 00H.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the flash address pointer L compare register (FLAPLC) to FFH.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Normal → <11>
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
• Internal verify 2
<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets flash address pointer L (FLAPL) to the start address.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets flash address pointer L compare register (FLAPLC) to the end address.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Normal → <11>
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
User’s Manual U18172EJ3V0UD
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