UPD78F9500MA-CAC-A Datasheet, PDF (337/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(14/15)
Page
Flash
memory
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect
command
register
The state of the pins in self programming mode is the same as that in HALT
mode.
p. 237
Since the security function set via on-board/off-board programming is disabled in
self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase processing
during self programming, set the protect byte.
p. 237
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address p. 237
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command, there is a possibility that device does not operate normally.
Clear the value of the FLCMD register to 00H immediately before setting self-
programming mode and normal operation mode.
p. 237
Cautions in the case of setting the self programming mode, refer to 16.8.2
Cautions on self programming function.
p. 238
Set the CPU clock so that it is 1 MHz or more during self programming.
p. 238
Execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, then execute self programming. At this
time, the HALT instruction is automatically released after 10 μs (MAX.) + 2 CPU
clocks (fCPU).
p. 238
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, wait for 8 μs after releasing the HALT
status, and then execute self programming.
p. 238
Clear the value of the FLCMD register to 00H immediately before setting self
programming mode and normal operation mode.
p. 238
Interrupt servicing cannot be executed in self-programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 = FFH) before
executing the specific sequence that sets self-programming mode and after
executing the specific sequence that changes the mode to the normal mode.
p. 239
PFS: Flash
Check FPRERR using a 1-bit memory manipulation instruction.
status register
p. 239
FLAPH, FLAPL: Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self p. 242
Flash address programming command. If the self programming command is executed with
pointers H and these bits set to 1, the device may malfunction.
L
FLAPHC,
Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self p. 242
FLAPLC: Flash programming command. If the self programming command is executed with
address pointer these bits set to 1, the device may malfunction.
H/L compare
registers
Set the number of the block subject to a block erase, verify, or blank check (same p. 242
value as FLAPH) to FLAPHC.
Shifting to self
programming
mode
Shifting to
normal mode
Byte write
Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank
check is performed.
Be sure to perform the series of operations described above using the user
program at an address where data is not erased or written.
If a write results in failure, erase the block once and write to it again.
p. 242
pp. 244,
245, 247,
248
p. 256
User’s Manual U18172EJ3V0UD
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