UPD78F9500MA-CAC-A Datasheet, PDF (100/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY)
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F
set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot
pulse output operation enable/disable, and output trigger of one-shot pulse by software.
TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of TOC00 to 00H.
Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FF63H After reset: 00H R/W
Symbol
7
<6>
<5>
TOC00
0
OSPT00 OSPE00
4
TOC004
<3>
LVS00
<2>
LVR00
1
TOC001
<0>
TOE00
OSPT00
0
1
One-shot pulse output trigger control via software
No one-shot pulse output trigger
One-shot pulse output trigger
OSPE00
0
1
One-shot pulse output operation control
Successive pulse output mode
One-shot pulse output mode^Note
TOC004
0
1
Timer output F/F control using match of CR010 and TM00
Disables inversion operation
Enables inversion operation
LVS00
0
0
1
1
LVR00
0
1
0
1
Timer output F/F status setting
No change
Timer output F/F reset (0)
Timer output F/F set (1)
Setting prohibited
TOC001
0
1
Timer output F/F control using match of CR000 and TM00
Disables inversion operation
Enables inversion operation
TOE00
0
1
Timer output control
Disables output (output fixed to level 0)
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.
Cautions 1. Timer operation must be stopped before setting other than OSPT00.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required, when OSPT00 is set to 1 successively.
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User’s Manual U18172EJ3V0UD