UPD78F9500MA-CAC-A Datasheet, PDF (165/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY)
Notes 3. Set the sampling time as follows.
• VDD ≥ 4.5 V: 1.0 μs or more
• VDD ≥ 4.0 V: 2.4 μs or more
• VDD ≥ 2.85 V: 3.0 μs or more
• VDD ≥ 2.7 V: 11.0 μs or more
4. Set the A/D conversion time as follows.
• VDD ≥ 4.5 V: 3.0 μs or more and less than 100 μs
• VDD ≥ 4.0 V: 4.8 μs or more and less than 100 μs
• VDD ≥ 2.85 V: 6.0 μs or more and less than 100 μs
• VDD ≥ 2.7 V: 14.0 μs or more and less than 100 μs
5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4.
6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 μs from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 μs or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the
first conversion result. If the ADCS is set to 1 without waiting for 1 μs or longer, ignore the first
conversion data.
ADCS
0
0
1
ADCE
0
1
×
Table 9-2. Settings of ADCS and ADCE
A/D Conversion Operation
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only comparator consumes power)
Conversion mode
Figure 9-4. Timing Chart When Comparator Is Used
ADCE
Comparator operating
Comparator
ADCS
Conversion
operation
Conversion
waiting
Conversion
operation
Note
Conversion stopped
Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 μs or longer to stabilize the
internal circuit.
Cautions 1.
2.
3.
4.
The above sampling time and conversion time do not include the clock frequency error.
Select the sampling time and conversion time such that Notes 3 and 4 above are satisfied,
while taking the clock frequency error into consideration (an error margin maximum of ±5%
when using the high-speed internal oscillator).
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
User’s Manual U18172EJ3V0UD
163