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| UPD78F9500MA-CAC-A Datasheet, PDF (291/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers | |||
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CHAPTER 18 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z AC CY
CMP
A, #byte
2
4 A â byte
ÃÃÃ
saddr, #byte
3
6 (saddr) â byte
ÃÃÃ
A, r
2
4 Aâr
ÃÃÃ
A, saddr
2
4 A â (saddr)
ÃÃÃ
A, !addr16
3
8 A â (addr16)
ÃÃÃ
A, [HL]
1
6 A â (HL)
ÃÃÃ
A, [HL + byte]
2
6 A â (HL + byte)
ÃÃÃ
ADDW
AX, #word
3
6 AX, CY â AX + word
ÃÃÃ
SUBW
AX, #word
3
6 AX, CY â AX â word
ÃÃÃ
CMPW
AX, #word
3
6 AX â word
ÃÃÃ
INC
r
2
4 râr+1
ÃÃ
saddr
2
4 (saddr) â (saddr) + 1
ÃÃ
DEC
r
2
4 rârâ1
ÃÃ
saddr
2
4 (saddr) â (saddr) â 1
ÃÃ
INCW
rp
1
4 rp â rp + 1
DECW
rp
1
4 rp â rp â 1
ROR
A, 1
1
2
(CY, A7 â A0, Amâ1 â Am) Ã 1
Ã
ROL
A, 1
1
2
(CY, A0 â A7, Am+1 â Am) Ã 1
Ã
RORC
A, 1
1
2
(CY â A0, A7 â CY, Amâ1 â Am) Ã 1
Ã
ROLC
A, 1
1
2
(CY â A7, A0 â CY, Am+1 â Am) Ã 1
Ã
SET1
saddr.bit
3
6 (saddr.bit) â 1
sfr.bit
3
6 sfr.bit â 1
A.bit
2
4 A.bit â 1
PSW.bit
3
6 PSW.bit â 1
ÃÃÃ
[HL].bit
2
10 (HL).bit â 1
CLR1
saddr.bit
3
6 (saddr.bit) â 0
sfr.bit
3
6 sfr.bit â 0
A.bit
2
4 A.bit â 0
PSW.bit
3
6 PSW.bit â 0
ÃÃÃ
[HL].bit
2
10 (HL).bit â 0
SET1
CY
1
2 CY â 1
1
CLR1
CY
1
2 CY â 0
0
NOT1
CY
1
2 CY â CY
Ã
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
Userâs Manual U18172EJ3V0UD
289
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