UPD78F9500MA-CAC-A Datasheet, PDF (153/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
8.4 Operation of Watchdog Timer
8.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by
option byte
The operation clock of watchdog timer is fixed to low-speed internal oscillation clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Low-speed internal oscillation clock
• Cycle: 2¹⁸/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.))
• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction^{Notes 1, 2}.
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1.
2.
The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to
bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
A status transition diagram is shown below
User’s Manual U18172EJ3V0UD
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