UPD78F9500MA-CAC-A Datasheet, PDF (330/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(7/15)
Page
8-bit timer PWM output
H1
Make sure that the CMP11 register setting value (M) and CMP01 register setting
value (N) are within the following range.
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
p. 141
Watchdog
timer
WDTM:
Watchdog timer
mode register
Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4
and WDCS3 respectively and the watchdog timer is stopped, then the internal
reset signal does not occur even if the following are executed.
p. 149
p. 150
• Second write to WDTM
• 1-bit memory manipulation instruction to WDTE
• Writing of a value other than “ACH” to WDTE
WDTM cannot be set by a 1-bit memory manipulation instruction.
p. 150
When using the flash memory programming by self programming, set the overflow p. 150
time for the watchdog timer so that enough overflow time is secured (Example 1-
byte writing: 200 μs MIN., 1-block deletion: 10 ms MIN.).
WDTE:
Watchdog timer
enable register
If a value other than ACH is written to WDTE, an internal reset signal is
generated.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
p. 150
p. 150
The value read from WDTE is 9AH (this differs from the written value (ACH)).
p. 150
When “low-
In this mode, operation of the watchdog timer cannot be stopped even during
speed internal STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-
oscillator cannot speed internal oscillation clock can be selected as the count source, so clear the
be stopped” is watchdog timer using the interrupt request of TMH1 before the watchdog timer
selected by
overflows after STOP instruction execution. If this processing is not performed,
option byte
an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
p. 151
When “low-
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
speed internal execution. After HALT/STOP mode is released, counting is started again using
oscillator can be the operation clock of the watchdog timer set before HALT/STOP instruction
stopped by
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
software” is
value.
selected by
option byte
p. 153
A/D
Sampling time
converter and A/D
(μPD78F9 ^{conversion time}
20x only)
Block Diagram
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 2 and 3
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
In μPD78F920x, VSS functions alternately as the ground potential of the A/D
converter. Be sure to connect VSS to a stabilized GND (= 0 V).
p. 158
p. 159
In μPD78F920x, VDD functions alternately as the A/D converter reference voltage p. 159
input. When using the A/D converter, stabilize VDD at the supply voltage used
(2.7 to 5.5 V).
ADM: A/D
converter mode
register
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 3 and 4
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
p. 163
328
User’s Manual U18172EJ3V0UD