UPD78F9500MA-CAC-A Datasheet, PDF (40/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
Figure 3-9. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Caution 1.
2.
Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP before using the stack memory.
Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can
be actually set.
0FF00H is in the SFR area, not the high-speed RAM area, so it was converted to 0FB00H
that is in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become
0FAFFH, but that value is not in the high-speed RAM area, so it is converted to 0FEFFH,
which is the same value as when 0FF00H is set to the stack pointer.
SP SP ^_ 2
SP ^_ 2
SP ^_ 1
SP
Figure 3-10. Data to Be Saved to Stack Memory
PUSH rp
instruction
Lower half
register pairs
Upper half
register pairs
SP SP ^_ 2
SP ^_ 2
SP ^_ 1
SP
CALL, CALLT
instructions
SP SP ^_ 3
SP ^_ 3
PC7 to PC0
SP ^_ 2
PC15 to PC8
SP ^_ 1
SP
Interrupt
PC7 to PC0
PC15 to PC8
PSW
Figure 3-11. Data to Be Restored from Stack Memory
POP rp
instruction
RET instruction
RETI instruction
SP
SP + 1
SP SP + 2
Lower half
register pairs
Upper half
register pairs
SP
SP + 1
SP SP + 2
PC7 to PC0
PC15 to PC8
SP
SP + 1
SP + 2
SP SP + 3
PC7 to PC0
PC15 to PC8
PSW
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User’s Manual U18172EJ3V0UD