UPD78F9500MA-CAC-A Datasheet, PDF (154/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
Figure 8-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped”
Is Selected by Option Byte
Reset
WDT clock: fRL
Overflow time: 546.13 ms (MAX.)
WDTE = “ACH”
Clear WDT counter.
WDT clock is fixed to fRL.
Select overflow time (settable only once).
WDT clock: fRL
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
HALT instruction
STOP instruction
Interrupt
Interrupt
HALT
WDT count continues.
STOP
WDT count continues.
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User’s Manual U18172EJ3V0UD