UPD78F9500MA-CAC-A Datasheet, PDF (288/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 18 INSTRUCTION SET OVERVIEW
18.2 Operation List
Mnemonic
Operand
Bytes Clocks
Operation
MOV
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
XCH
A, X
A, r
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL, byte]
Notes 1. Except r = A.
2. Except r = A, X.
3
3
3
Note 1
2
Note 1
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
Note 2
2
2
2
1
1
2
6 r ← byte
6 (saddr) ← byte
6 sfr ← byte
4 A←r
4 r←A
4 A ← (saddr)
4 (saddr) ← A
4 A ← sfr
4 sfr ← A
8 A ← (addr16)
8 (addr16) ← A
6 PSW ← byte
4 A ← PSW
4 PSW ← A
6 A ← (DE)
6 (DE) ← A
6 A ← (HL)
6 (HL) ← A
6 A ← (HL + byte)
6 (HL + byte) ← A
4 A↔X
6 A↔r
6 A ↔ (saddr)
6 A ↔ sfr
8 A ↔ (DE)
8 A ↔ (HL)
8 A ↔ (HL + byte)
Flag
Z AC CY
×××
×××
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
286
User’s Manual U18172EJ3V0UD