UPD78F9500MA-CAC-A Datasheet, PDF (333/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(10/15)
Page
A/D
converter
(μPD78F9
20x only)
A/D conversion
result register
(ADCR,
ADCRH) read
operation
When a write operation is performed to the A/D converter mode register (ADM) p. 175
and analog input channel specification register (ADS), the contents of ADCR and
ADCRH may become undefined. Read the conversion result following
conversion completion before writing to ADM and ADS. Using a timing other
than the above may cause an incorrect conversion result to be read.
Interrupt
functions
The operating
current at the
conversion
waiting mode
IF0: Interrupt
request flag
registers,
MK0: Interrupt
mask flag
registers
The DC characteristic of the operating current at the STOP mode is not satisfied
at the conversion waiting mode (when A/D converter mode register (ADM) is set
up with bit 7(ADCS) =0 and bit 0 (ADCE) =1) (only comparator consumes
power).
p. 175
Because P21 and P32 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port
function, an interrupt request flag is set. Therefore, the interrupt mask flag
should be set to 1 before using the output mode.
pp. 179,
180
INTM0: External Be sure to clear bits 0, 1, 6, and 7 to 0.
interrupt mode _{Before setting the INTM0 register, be sure to set the corresponding interrupt}
register 0
mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register,
clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag
(××MK× = 0), which will enable interrupts.
p. 181
p. 181
Interrupt
requests are
held pending
Interrupt requests will be held pending while the interrupt request flag registers p. 183
(IF0) or interrupt mask flag registers (MK0) are being accessed.
Standby
function
Interrupt
Multiple interrupts can be acknowledged even for low-priority interrupts.
request pending
p. 184
−
The LSRSTOP setting is valid only when “Can be stopped by software” is set for p. 186
the low-speed internal oscillator by the option byte.
STOP mode
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed internal oscillation clock).
p. 187
STOP mode,
HALT mode
The following sequence is recommended for operating current reduction of the p. 187
A/D converter in μPD78F920x when the standby function is used: First clear bit 7
(ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop
the A/D conversion operation, and then execute the HALT or STOP instruction.
STOP mode
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 11-1).
p. 187
OSTS:
Oscillation
stabilization
time select
register
(μPD78F920x
only)
To set and then release the STOP mode, set the oscillation stabilization time as p. 188
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
set by OSTS
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
p. 188
The oscillation stabilization time that elapses on power application or after
p. 188
release of reset is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
User’s Manual U18172EJ3V0UD
331