UPD78F9500MA-CAC-A Datasheet, PDF (202/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 12 RESET FUNCTION
Figure 12-4. Reset Timing by RESET Input in STOP Mode
<1> With high-speed internal oscillation clock or external clock input
STOP instruction is executed.
High-speed internal oscillation clock or
external clock input
CPU clock
Normal
operation
in progress
RESET
Stop status
Reset period
(oscillation stops) (oscillation stops)
Internal reset signal
Port pin
Delay
100 ns (TYP.)
Delay
100 ns (TYP.)
Normal operation (reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Hi-Z
Note The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
<R>
<2> With crystal/ceramic oscillation clock (μPD78F920x only)
STOP instruction is executed.
Crystal/ceramic
oscillation clock
Normal
CPU clock operation
in progress
RESET
Stop status
Reset period
(oscillation stops) (oscillation stops)
Oscillation stabilization
time (2¹⁰/fX to 2¹⁷/fX)
Normal operation
(reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Internal reset signal
Port pin
Delay
100 ns (TYP.)
Delay
100 ns (TYP.)
Hi-Z
Note The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 13
POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR.
2. fX: System clock oscillation frequency
200
User’s Manual U18172EJ3V0UD