UPD78F9500MA-CAC-A Datasheet, PDF (183/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 10 INTERRUPT FUNCTIONS
Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable
interrupts.
(4) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically saved to a stack,
and the IE flag is reset to 0.
Reset signal generation sets PSW to 02H.
Figure 10-5. Program Status Word (PSW) Configuration
Symbol 7
6
5
4
3
2
1
0
PSW IE Z
0 AC 0
0
1 CY
After reset
02H
IE
0 Disabled
1 Enabled
Used in the execution of ordinary instructions
Whether to enable/disable interrupt acknowledgment
10.4 Interrupt Servicing Operation
10.4.1 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to
1), then the request is acknowledged as a vector interrupt.
The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is
shown in Table 10-3.
See Figures 10-7 and 10-8 for the interrupt request acknowledgment timing.
Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
Maximum Time^Note
9 clocks
19 clocks
Note The wait time is maximum when an interrupt
request is generated immediately before BT and
BF instructions.
1
Remark 1 clock: _fCPU (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
User’s Manual U18172EJ3V0UD
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