UPD78F9500MA-CAC-A Datasheet, PDF (216/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 14 LOW-VOLTAGE DETECTOR
Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
<2>
LVIMK flag
(set by software)
<1>
Note 1
<7> Cleared by software
LVION flag
(set by software)
<3>
<4> 0.2 ms or longer
LVIF flag
INTLVI
<5>
Note 2
Time
LVIIF flag
Internal reset signal
Note 2
<6>
Note 2 Cleared by software
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. An interrupt request signal (INTLVI) may be generated, and the LVIF and LVIIF flags may be set to 1.
Remark <1> to <7> in Figure 14-5 above correspond to <1> to <7> in the description of “when starting operation”
in 14.4 (2) When used as interrupt.
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User’s Manual U18172EJ3V0UD