UPD78F9500MA-CAC-A Datasheet, PDF (325/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(2/15)
Page
Port
P21, P32
functions
PMC2: Port
mode control
register 2
(μPD78F920x
only)
−
Main clock OSTS:
Oscillation
stabilization
time select
register
(μPD78F920x
only)
Crystal/
−
ceramic
oscillator
(μPD78F9
20x only)
16-bit
TM00: 16-bit
timer/
timer counter
event
00
counters
00
CR000: 16-bit
(μPD78F9 _{timer capture/}
20x only) _compare
register 000
Because P21 and P32 are also used as external interrupt pins, the corresponding
interrupt request flag is set if each of these pins is set to the output mode and its
output level is changed. To use the port pin in the output mode, therefore, set the
corresponding interrupt mask flag to 1 in advance.
p. 67
When PMC20 to PMC23 are set to 1, the port function on the P20/ANI0 to
P23/ANI3 pins cannot be used. Moreover, be sure to set the pull-up resistor
option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode.
p. 69
Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a
port in 8-bit units. Therefore, the contents of the output latch of a pin in the input
mode, even if it is not subject to manipulation by the instruction, are undefined in
a port with a mixture of inputs and outputs.
p. 71
To set and then release the STOP mode, set the oscillation stabilization time as p. 78
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time
set by OSTS
The wait time after the STOP mode is released does not include the time from the p. 78
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset input or interrupt
generation.
The oscillation stabilization time that elapses on power application or after release p. 78
of reset is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
When using the crystal/ceramic oscillator, wire as follows in the area enclosed by p. 79
the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring
near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential
as VSS. Do not ground the capacitor to a ground pattern through which a high
current flows.
• Do not fetch signals from the oscillator.
Even if TM00 is read, the value is not captured by CR010.
pp. 92,
124
When TM00 is read, count misses do not occur, since the input of the count clock pp. 92,
is temporarily stopped and then resumed after the read.
124
Set CR000 to other than 0000H in the clear & start mode entered on match
pp. 93,
between TM00 and CR000. This means a 1-pulse count operation cannot be
124
performed when this register is used as an external event counter. However, in
the free-running mode and in the clear & start mode using the valid edge of the
TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
when CR000 changes from 0000H to 0001H following overflow (FFFFH).
If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00),
TM00 continues counting, overflows, and then starts counting from 0 again. If the
new value of CR000 is less than the old value, therefore, the timer must be reset
to be restarted after the value of CR000 is changed.
pp.93,
124
User’s Manual U18172EJ3V0UD
323