UPD78F9500MA-CAC-A Datasheet, PDF (200/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 12 RESET FUNCTION
Figure 12-2. Timing of Reset by RESET Input
<1> With high-speed internal oscillation clock or external clock input
High-speed internal oscillation clock or
external clock input
CPU clock
RESET
Normal operation
in progress
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Internal reset signal
Port pin
Delay
100 ns (TYP.)
Delay
100 ns (TYP.)
Hi-Z
Note The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
<R>
<2> With crystal/ceramic oscillation clock (μPD78F920x only)
Crystal/ceramic
oscillation clock
RESET
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (2¹⁰/fX to 2¹⁷/fX)
Normal operation
(reset processing, CPU clock)
Operation stops because option
byte is referenced^Note.
Internal reset signal
Port pin
Delay
100 ns (TYP.)
Delay
100 ns (TYP.)
Hi-Z
Note The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
Remark fX: System clock oscillation frequency
198
User’s Manual U18172EJ3V0UD