UPD78F9500MA-CAC-A Datasheet, PDF (147/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 7 8-BIT TIMER H1
Figure 7-10. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H)
Count clock
8-bit timer counter H1 00H 01H 02H 80H A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
CMP01
A5H
CMP11
TMHE1
02H
<2>
02H (03H)
03H
<2>'
INTTMH1
TOH1
(TOLEV1 = 0)
<1>
<3>
<4>
<5>
<6>
<1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count
clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0).
<2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1
is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output.
<4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to
the CMP11 register and the CMP11 register value is changed (<2>’).
However, three count clocks or more are required from when the CMP11 register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output
becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.
<6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.
User’s Manual U18172EJ3V0UD
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