UPD78F9500MA-CAC-A Datasheet, PDF (188/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 11 STANDBY FUNCTION
11.1 Standby Function and Configuration
11.1.1 Standby function
Table 11-1. Relationship Between Operation Clocks in Each Operation Status
Status
Operation Mode
Note 1
Low-Speed Internal Oscillator
Note 2
LSRSTOP = 0
LSRSTOP = 1
System Clock
Clock Supplied to
Peripheral
Hardware
Reset
STOP
Stopped
Oscillating
Oscillating^{Note 3}
Stopped
Stopped
Stopped
HALT
Oscillating
Oscillating
Notes 1.
2.
3.
When “Cannot be stopped” is selected for low-speed internal oscillator by the option byte.
When it is selected that the low-speed internal oscillator “can be stopped by software”, oscillation of the
low-speed internal oscillator can be stopped by LSRSTOP.
If the operating clock of the watchdog timer is the low-speed internal oscillation clock, the watchdog
timer is stopped.
Caution The LSRSTOP setting is valid only when “Can be stopped by software” is set for the low-speed
internal oscillator by the option byte.
Remark LSRSTOP: Bit 0 of the low-speed internal oscillation mode register (LSRCM)
The standby function is designed to reduce the operating current of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
Oscillation of the system clock oscillator continues. If the low-speed internal oscillator is operating before the
HALT mode is set, oscillation of the clock of the low-speed internal oscillator continues (refer to Table 11-1.
Oscillation of the low-speed internal oscillation clock (whether it cannot be stopped or can be stopped by
software) is set by the option byte). In this mode, the operating current is not decreased as much as in the
STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request
generation and frequently carrying out intermittent operations.
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User’s Manual U18172EJ3V0UD