UPD78F9500MA-CAC-A Datasheet, PDF (86/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 5 CLOCK GENERATORS
<R> (2) Crystal/ceramic oscillator (μPD78F920x only)
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected
and the accuracy of processing is improved because the frequency deviation is small, as compared with high-
speed internal oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator (μPD78F920x Only)
(a)
VDD
RESET _H
Internal reset
System clock
CPU clock
(b)
(c)
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stops^{Note 1})
Clock oscillation
stabilization
time^{Note 2}
Notes 1. Operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to
CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is
released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
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User’s Manual U18172EJ3V0UD