UPD78F9500MA-CAC-A Datasheet, PDF (331/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(8/15)
Page
A/D
ADM: A/D
converter converter mode
(μPD78F9 ^register
20x only)
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped
(ADCS = 0) and then A/D conversion is started, execute two NOP instructions or
an instruction equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
p. 163
p. 163
Be sure to clear bits 6, 2, and 1 to 0.
p. 163
ADS: Analog
input channel
specification
register
Be sure to clear bits 2 to 7 of ADS to 0.
p. 164
ADCR: 10-bit
A/D conversion
result register
When writing to the A/D converter mode register (ADM) and analog input channel p. 164
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
PMC2: Port
mode control
register 2
If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1,
P21/ANI1/TIO10/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for
any purpose other than the A/D converter function.
Be sure to set 0 to the Pull-up resistor option register of the pin set in A/D
converter mode.
p. 165
A/D converter Make sure the period of <1> to <4> is 1 μs or more.
operations
pp. 166,
170
It is no problem if the order of <1> and <2> is reversed.
pp. 166,
170
<1> can be omitted. However, ignore the data resulting from the first conversion p. 170
after <4> in this case.
The period from <5> to <8> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set
using FR2 to FR0.
p. 170
Operating
To satisfy the DC characteristics of supply current in STOP mode, clear bit 7
current in STOP (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before
mode
executing the STOP instruction.
p. 173
Input range of
ANI0 to ANI3
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of VDD or
higher and VSS or lower (even in the range of absolute maximum ratings) is input
to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
p. 173
Conflicting
operations
Conflict between A/D conversion result register (ADCR, ADCRH) write and
ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH
read has priority. After the read operation, the new conversion result is written to
ADCR, ADCRH.
p. 173
Conflict between ADCR, ADCRH write and A/D converter mode register (ADM)
write or analog input channel specification register (ADS) write upon the end of
conversion ADM or ADS write has priority. ADCR, ADCRH write is not
performed, nor is the conversion end interrupt signal (INTAD) generated.
p. 173
User’s Manual U18172EJ3V0UD
329