UPD78F9500MA-CAC-A Datasheet, PDF (197/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

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CHAPTER 11 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 11-6. STOP Mode Release by Reset signal generation
(1) If CPU clock is high-speed internal oscillation clock or external input clock
STOP
instruction
Reset signal
CPU status
Operation
mode
System clock
oscillation
Oscillation
STOP mode
Reset Operation
period stops^Note.
Oscillation stops.
Operation mode
Oscillation
Note Operation is stopped (277 μs (MIN.), 544 μs (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) If CPU clock is crystal/ceramic oscillation clock (μPD78F920x only)
STOP
instruction
Reset signal
CPU status
Operation
mode
System clock
oscillation
Oscillation
STOP mode
Reset Operation Oscillation _Operation
period stops^Note. stabilization waits _mode
Oscillation stops.
Oscillation
Oscillation stabilization time
(2¹⁰/fX to 2¹⁷/fX)
Note Operation is stopped (276 μs (MIN.), 544 μs (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark fX: System clock oscillation frequency
Table 11-5. Operation in Response to Interrupt Request in STOP Mode
Release Source
Maskable interrupt request
Reset signal generation
×: don’t care
MK××
0
0
1
−
IE
Operation
0 Next address instruction execution
1 Interrupt servicing execution
× STOP mode held
× Reset processing
User’s Manual U18172EJ3V0UD
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