UPD78F9500MA-CAC-A Datasheet, PDF (292/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 18 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z AC CY
CALL
!addr16
3
6
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
[addr5]
1
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
6
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
1
8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
RRR
PUSH
PSW
1
2 (SP − 1) ← PSW, SP ← SP − 1
rp
1
4
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
POP
PSW
1
4 PSW ← (SP), SP ← SP + 1
RRR
rp
1
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
MOVW
SP, AX
2
8 SP ← AX
AX, SP
2
6 AX ← SP
BR
!addr16
3
6 PC ← addr16
$addr16
2
6 PC ← PC + 2 + jdisp8
AX
1
6
PCH ← A, PCL ← X
BC
$saddr16
2
6 PC ← PC + 2 + jdisp8 if CY = 1
BNC
$saddr16
2
6 PC ← PC + 2 + jdisp8 if CY = 0
BZ
$saddr16
2
6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$saddr16
2
6 PC ← PC + 2 + jdisp8 if Z = 0
BT
saddr.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
8 PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
BF
saddr.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
8 PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16
4
10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
DBNZ
B, $addr16
2
6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
3
8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
1
2 No Operation
EI
3
6 IE ← 1 (Enable Interrupt)
DI
3
6 IE ← 0 (Disable Interrupt)
HALT
1
2 Set HALT Mode
STOP
1
2 Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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User’s Manual U18172EJ3V0UD