UPD78F9500MA-CAC-A Datasheet, PDF (193/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

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CHAPTER 11 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 11-3. HALT Mode Release by Reset Signal Generation
(1) When CPU clock is high-speed internal oscillation clock or external input clock
HALT
instruction
Reset signal
CPU status
Operation
mode
HALT mode
System clock
oscillation
Oscillates
Reset Operation
period stops^Note
Oscillation stops
Operation mode
Oscillates
Note Operation is stopped (277 μs (MIN.), 544 μs (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) When CPU clock is crystal/ceramic oscillation clock (μPD78F920x only)
HALT
instruction
Reset signal
CPU status
System clock
oscillation
Operation
mode
HALT mode
Oscillates
Reset Operation Oscillation Operation
period stops^Note stabilization waits mode
Oscillation stops
Oscillates
Oscillation stabilization time
(2¹⁰/fX to 2¹⁷/fX)
Note Operation is stopped (276 μs (MIN.), 544 μs (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark fX: System clock oscillation frequency
Table 11-3. Operation in Response to Interrupt Request in HALT Mode
Release Source
Maskable interrupt request
Reset signal generation
×: don’t care
MK××
0
0
1
−
IE
Operation
0 Next address instruction execution
1 Interrupt servicing execution
× HALT mode held
× Reset processing
User’s Manual U18172EJ3V0UD
191