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| UPD78F9500MA-CAC-A Datasheet, PDF (290/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers | |||
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CHAPTER 18 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z AC CY
SUBC
A, #byte
2
4 A, CY â A â byte â CY
ÃÃÃ
saddr, #byte
3
6 (saddr), CY â (saddr) â byte â CY
ÃÃÃ
A, r
2
4 A, CY â A â r â CY
ÃÃÃ
A, saddr
2
4 A, CY â A â (saddr) â CY
ÃÃÃ
A, !addr16
3
8 A, CY â A â (addr16) â CY
ÃÃÃ
A, [HL]
1
6 A, CY â A â (HL) â CY
ÃÃÃ
A, [HL + byte]
2
6 A, CY â A â (HL + byte) â CY
ÃÃÃ
AND
A, #byte
2
4 A â A ⧠byte
Ã
saddr, #byte
3
6 (saddr) â (saddr) ⧠byte
Ã
A, r
2
4 AâAâ§r
Ã
A, saddr
2
4 A â A ⧠(saddr)
Ã
A, !addr16
3
8 A â A ⧠(addr16)
Ã
A, [HL]
1
6 A â A ⧠(HL)
Ã
A, [HL + byte]
2
6 A â A ⧠(HL + byte)
Ã
OR
A, #byte
2
4 A â A ⨠byte
Ã
saddr, #byte
3
6 (saddr) â (saddr) ⨠byte
Ã
A, r
2
4 AâAâ¨r
Ã
A, saddr
2
4 A â A ⨠(saddr)
Ã
A, !addr16
3
8 A â A ⨠(addr16)
Ã
A, [HL]
1
6 A â A ⨠(HL)
Ã
A, [HL + byte]
2
6 A â A ⨠(HL + byte)
Ã
XOR
A, #byte
2
4 A â A ⨠byte
Ã
saddr, #byte
3
6 (saddr) â (saddr) ⨠byte
Ã
A, r
2
4 AâAâ¨r
Ã
A, saddr
2
4 A â A ⨠(saddr)
Ã
A, !addr16
3
8 A â A ⨠(addr16)
Ã
A, [HL]
1
6 A â A ⨠(HL)
Ã
A, [HL + byte]
2
6 A â A ⨠(HL + byte)
Ã
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
288
Userâs Manual U18172EJ3V0UD
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