UPD78F9500MA-CAC-A Datasheet, PDF (157/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 8 WATCHDOG TIMER
8.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by
software” is selected by option byte)
The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or
low-speed internal oscillation clock is being used.
(1) When the watchdog timer operation clock is the system clock (fX) when the STOP instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
operation stops for 34 μs (TYP.) (after waiting for the oscillation stabilization time set by the oscillation
stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then
counting is started again using the operation clock before the operation was stopped. At this time, the counter is
not cleared to 0 but holds its value.
Figure 8-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
<R>
<1> CPU clock: Crystal/ceramic oscillation clock (μPD78F920x Only)
Normal
CPU operation operation
fCPU
Watchdog timer
Operating
STOP
Operation
stopped^Note Oscillation stabilization time
Oscillation stopped
Oscillation stabilization time
(set by OSTS register)
Operation stopped
Normal operation
Operating
<2> CPU clock: High-speed internal oscillation clock or external clock input
CPU operation
Normal
operation
STOP
Operation
stopped^Note
Normal operation
fCPU
Watchdog timer
Oscillation stopped
Operating
Operation stopped
Operating
Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).
User’s Manual U18172EJ3V0UD
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