UPD78F9500MA-CAC-A Datasheet, PDF (334/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(11/15)
Page
Standby
function
Reset
function
Power-
on-clear
circuit
Low-
voltage
detector
HALT mode
setting and
operating
statuses
STOP mode
setting and
operating
statuses
−
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
clear, the standby mode is immediately cleared if set.
p. 189
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, in the STOP mode,
the normal operation mode is restored after the STOP instruction is executed and
then the operation is stopped for 34 μs (TYP.) (after an additional wait time for
stabilizing the oscillation set by the oscillation stabilization time select register
(OSTS) has elapsed when crystal/ceramic oscillation is used).
p. 192
For an external reset, input a low level for 2 μs or more to the RESET pin.
p. 196
Timing of reset
by overflow of
watchdog timer
RESF: Reset
control flag
register
Functions of
power-on-clear
circuit
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detect
register
LVIS: Low-
voltage
detection level
select register
When used as
reset
During reset signal generation, the system clock and low-speed internal oscillation p. 196
clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ is
reset if a low level is input to the RESET pin after reset is released by the POC
circuit, the LVI circuit and the watchdog timer and before the option byte is
referenced again. The reset status is retained until a high level is input to the
RESET pin.
p. 196
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
p. 197
The watchdog timer is also reset in the case of an internal reset of the watchdog p. 199
timer.
Do not read data by a 1-bit memory manipulation instruction.
p. 203
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
p. 204
Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V ±0.1 p. 204
V, use a voltage in the range of 2.2 to 5.5 V.
In a system where the supply voltage (VDD) fluctuates for a certain period in the
vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
p. 206
To stop LVI, follow either of the procedures below.
p. 209
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Be sure to set bits 2 to 6 to 0.
p. 209
Bits 4 to 7 must be set to 0.
p. 210
If a value other than the above is written during LVI operation, the value becomes p. 210
undefined at the very moment it is written, and thus be sure to stop LVI (bit
7(LVION) = 0 on the LVIM register) before writing.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
p. 211
If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIM is set to 1, an internal p. 211
reset signal is not generated.
332
User’s Manual U18172EJ3V0UD