UPD78F9500MA-CAC-A Datasheet, PDF (185/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 10 INTERRUPT FUNCTIONS
Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last
Clock During Instruction Execution)
Clock
8 clocks
CPU
NOP
MOV A, r
Saving PSW and PC, jump
to interrupt servicing
Interrupt
servicing
program
Interrupt
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing
starts after the next instruction is executed.
Figure 10-8 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is
set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is
executed, and then the interrupt acknowledgment processing is performed.
Caution Interrupt requests will be held pending while the interrupt request flag register 0 (IF0) or
interrupt mask flag register 0 (MK0) are being accessed.
10.4.2 Multiple interrupt servicing
In order to perform multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is
being serviced, the interrupt mask function must be used to mask interrupts for which a low priority is to be set.
User’s Manual U18172EJ3V0UD
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