UPD78F9500MA-CAC-A Datasheet, PDF (328/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

Function
Details of
Function
APPENDIX D LIST OF CAUTIONS
Cautions
(5/15)
Page
16-bit
PRM00:
timer/
Prescaler mode
event
register 00
counters
00
(μPD78F9
20x only)
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is fXP, and in the latter case the count clock is selected by
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
pp. 100,
129
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a pp. 100,
timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be 129
used as the input pin (TI010) of the valid edge.
Interval timer
Changing the CR000 setting during TM00 operation may cause a malfunction. To p. 101
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
External event When reading the external event counter count value, TM00 should be read.
counter
pp. 105,
129
Pulse width
To use two capture registers, set the TI000 and TI010 pins.
measurement
pp. 106,
127
The measurable pulse width in this operation example is up to 1 cycle of the timer pp. 106,
counter.
108, 110,
112
Square-wave
output
Changing the CR000 setting during TM00 operation may cause a malfunction. To p. 114
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
PPG output
Changing the CRC0n0 setting during TM00 operation may cause a malfunction.
To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
p. 116
Values in the following range should be set in CR000 and CR010.
pp. 117,
0000H < CR010 < CR000 ≤ FFFFH
129
The cycle of the pulse generated through PPG output (CR000 setting value + 1) pp. 117,
has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
129
One-shot pulse Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To pp. 119,
output: software output the one-shot pulse again, wait until the current one-shot pulse output is
125
trigger
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin. Because the external trigger is valid even in this case, the timer is
cleared and started even at the level of the TI000 pin or its alternate-function port
pin, resulting in the output of a pulse at an undesired timing.
pp. 119,
125
Do not set 0000H to the CR000 and CR010 registers.
pp. 120,
126
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
pp. 121,
124
One-shot pulse Do not input the external trigger again while the one-shot pulse is output. To
output: external output the one-shot pulse again, wait until the current one-shot pulse output is
trigger
completed.
pp. 121,
126
Do not set the CR000 and CR010 registers to 0000H.
pp. 122,
126
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC002 and TMC003 bits.
pp. 123,
124
326
User’s Manual U18172EJ3V0UD