UPD78F9500MA-CAC-A Datasheet, PDF (175/342 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcontrollers

CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY)
9.6 Cautions for A/D Converter
(1) Supply current in STOP mode
To satisfy the DC characteristics of supply current in STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 before executing the STOP instruction.
(2) Input range of ANI0 to ANI3
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of VDD or higher and VSS or lower (even in
the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by
instruction upon the end of conversion
ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,
ADCRH.
<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt
signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the VDD pin and ANI0 to ANI3 pins.
<1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply.
<2> Because the effect increases in proportion to the output impedance of the analog input source, it is
recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise.
<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during
conversion.
<4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts.
Reference
voltage
input
Figure 9-19. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than VDD or
equal to or lower than VSS may enter, clamp with a diode with a
small VF value (0.3 V or lower).
VDD
C = 0.01 to 0.1 μF
ANI0 to ANI3
VSS
User’s Manual U18172EJ3V0UD
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