M16C30P_07 Datasheet, PDF (98/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
13. DMAC
Table 13.1 DMAC Specifications
Item
No. of Channels
Transfer Memory Space
Maximum No. of Bytes Transferred
DMA Request Factors ^{(1, 2)}
Channel Priority
Transfer Unit
Transfer Address Direction
Transfer Mode Single Transfer
Repeat Transfer
DMA Interrupt Request Generation Timing
DMA Start up
DMA Shutdown Single Transfer
Repeat Transfer
Reload Timing for Forward Address Pointer
and Transfer Counter
DMA Transfer Cycles
Specification
2 (cycle steal method)
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A2 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter (i = 0 to 1)
underflows after reaching the terminal count.
When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register = 1 (enabled).
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1”
(enabled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Minimum 3 cycles between SFR and internal RAM
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt
control register.
2. The selectable factors of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
Rev.1.22 Mar 29, 2007 Page 82 of 291
REJ09B0179-0122