M16C30P_07 Datasheet, PDF (158/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
15. Serial Interface
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count
source
RE bit in UiC1
register
RXDi
Transfer clock
RI bit in UiC1
register
RTSi
IR bit in SiRIC
register
“1”
“0”
Stop bit
Start bit
D0
D1 D7
Sampled “L”
Receive data taken in
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive
register to UiRB register
Set to “0” by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 15.19 Receive Operation
15.1.2.1 Bit Rate
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table
15.9 lists Example of Bit Rates and Settings.
Table 15.9 Example of Bit Rates and Settings
Bit Rate (bps)
Count Source of UiBRG
1200
f8
2400
f8
4800
f8
9600
f1
14400
f1
19200
f1
28800
f1
31250
f1
38400
f1
51200
f1
Peripheral Function Clock : 16MHz
Set Value of UiBRG : n
Bit Rate (bps)
103 (67h)
1202
51 (33h)
2404
25 (19h)
4808
103 (67h)
9615
68 (44h)
14493
51 (33h)
19231
34 (22h)
28571
31 (1Fh)
31250
25 (19h)
38462
19 (13h)
50000
Rev.1.22 Mar 29, 2007 Page 142 of 291
REJ09B0179-0122