M16C30P_07 Datasheet, PDF (108/317 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/30 SERIES

M16C/30P Group
14. Timers
14. Timers
Six 16-bit timers, each capable of operating independently of the others, can be classified by function as either Timer
A (three) and Timer B (three). The count source for each timer acts as a clock, to control such timer operations as
counting, reloading, etc. Figures 14.1 and 14.2 show block diagrams of Timer A and Timer B configuration,
respectively.
f2 _{PCLK0 bit =0}
1/2
• Main clock ^f1
1/8
PCLK0 bit =1
f1 or f2
f8
XCIN
Clock prescaler
1/32
Reset
fC32
1/4
f32
Set the CPSR bit in the
CPSRF register to “1”
(= prescaler reset)
f1 or f2 f8 f32 fC32
TA0IN
TCK1 to TCK0
00
01
10
11
Noise
filter
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 to TMOD0
Timer A0
01
00
01: Event counter mode
11 _{TA0TGH to TA0TGL}
Timer A0 interrupt
TA1IN
00TCK1 ^{to TCK0}
01
10
11
Noise
filter
00: Timer mode
10: One-shot timer mode
11: PWM mode
10
TMOD1 to TMOD0
Timer A1
01
00
01: Event counter mode
11 _{TA1TGH to TA1TGL}
Timer A1 interrupt
TA2IN
TCK1 to TCK0
00
01
10
11
Noise
filter
00: Timer mode
10: One-shot timer mode
11: PWM mode
10
TMOD1 to TMOD0
Timer A2
01
00
01: Event counter mode
11 _{TA2TGH to TA2TGL}
Timer A2 interrupt
Timer B2 overflow
or underflow
Figure 14.1 Timer A Configuration
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 2)
TAiGH to TAiGL: Bits in ONSF register and TRGSR register
Rev.1.22 Mar 29, 2007 Page 92 of 291
REJ09B0179-0122